[seancostello]

Could an FPGA be used to aid with getting data out of the SDRAM and into the DSP / local SRAM system? Maybe with modulo math?

Of course, if you have an FPGA doing the delay line management with the cheaper chips, it would be tempting to create a full reverb solution based around said FPGA.

This conversation is reminding me of having to deal with the 2126x SHARCs during the ADI days, before the 21369 came out. The 2126x chips had the memory access pins removed, due to some large customer requesting this. So all external memory access had to go through DMA, which was horribly slow. The block based processing helped a little, but not much. The Blackfin DSPs were coming out at that time, and were viewed as underachievers for audio by most of the higher ups at ADI. In our little group, we were able to get much higher performance out of the Blackfins than the 2126x for delay based algorithms. The 2136x series restored the memory access pins, thus saving face for the SHARC line.