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Originally Posted by _rd  Just to nitpick, VHDL is not used to "program", it is used to "describe". It is a hardware description language. |
You are absolutely correct that these class of languages are 'description languages'. However stuff like Verilog and VHDL is generally considered to be a type of 'programming language' due to the use of the term 'programmable logic devices'. It doesnt really matter. who cares.