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Originally Posted by seancostello  In all seriousness, isn't 248k x24bits about 5 seconds of fast delay memory @ 48 kHz? Older reverb designs got by just fine with about 1 second of delay memory; double or triple that and things can sound really nice. I would doubt that a single Freescale DSP would have the cycles to fill up 15 seconds of memory with enough taps / allpasses / whatever to get the required echo density. |
That, and memory bandwidth, too. I'm not sure what the performance of some of these ADI DSP's are, but the 56k seems slow. The only reason that I am sticking to it is relative ease of programming, cheapness of dev tools, and not insignificantly, ease of soldering a prototype together. BGA's offer great packaging density but prototyping is a bit of a bear. I'm actually having a problem finding 1.8V SDRAM in TSOP packaging - I can find 90-ball BGA's but I don't want to solder those down. Level-shifting takes too long on a high-speed bus and I don't want the extra time delays.
I just did up a brute-force reverb using two strings of about 25 or so allpasses in a row followed by a single-pole HF rolloff filter. Eight of the allpasses modulate. It's a bit unnatural but huge sounding. About 50 allpasses and eight modulations take about 10 microseconds and I'm running the processor at 96 MHz, and one wait state to delay RAM. Cascaded allpasses could be written more efficiently, because I wrote my allpass to assume that take a delay line and run the input into the allpass, then write the output back to RAM. I think cascaded allpasses could have about double the throughput if I optimized things for cascading without delays between them.
The processor can run at 120 MHz but I run it a bit slower because at 120 MHz I run out of setup time for the SRAM address and I would have to add one wait state which would slow things down. The 56720 would not have that problem as with that much RAM on-chip, I could run full-tilt and not worry about wait states. Ahh, the life of the hardware designer.
-Dale