| The assembler doesn't - the DSP56300 pipeline scheduler does that for you, but the assembler does warn you. But I did up a quick multitap delay and a few delay loops and allpasses, and found that the actual application speed (in terms of all-passes or taps or filters or loops) is about triple that of the AL3201 that I'm used to - and multitaps are quite quick, actually. I am looking at modifying my multitap algorithm to alternate taps, requiring an even number of taps, but doing MAC's to both accumulators, and summing the two up at the end. That would make taps pretty cheap - probably three clock cycles per tap. If you were looking for a straight FIR-based multitap delay, you could do 500 taps that way per sample. Or a 'convolution' of 10 milliseconds. I'd probably offer both algorithms - one for 4 or fewer where it's cheaper not to take the cycles to sum at the end.
The DSP56k is not nearly as impressive as the ADI Tigersharc or any of the VLIW processors in terms of performance, but reasonably easy to work with for a DIY box. |