Quote:
Originally Posted by triez  I didn't know that.... But how does a system with an 8 meg clock shift data at 400Mb per second? |
It it an 8kHz (not MHz) clock - but this isn't the data clock - it is the clock that starts a new bus cycle. Clearly the data rate is much higher, and inside any 125 microsecond period a lot of data transfers can occur, and a lot of data moved.
What is also interesting is that the 8kHz clock is retained across all FW speeds - but of course with higher speeds the data rate is higher.
When the bus reconfigures a cycle master is selected - and it can be any device that wants to be the master. This allows FW audio converters to request that they become the sample rate master clock. The cycle clock can then be used as a clock distribution system to any other converter as well. But the ability of a FW audio device to retain the sample clock inside itself is a big win for audio quality.