| There's nothing wrong with the built in decimation filter. It seems to me that the best place to implement some kind of limiting process would be after the modulator output, when the signal is still "oversampled". It is in this realm that non-linear processing (limiting/compression) can be accomplished and artifacts from such processing be pushed outside the audible band and filtered out afterwards (it's mostly high frequency content/harmonics, so we use low pass filtering). Of course, we are not really "limiting" the input(analog) signal, since once the maximum amplitude of the a/d input is exceeded we have "lost" information, that is, you can't go above "1" for ONE SAMPLE, for a 1-bit converter, but because the signal is OVERSAMPLED we can "bring it (the signal at some arbitrary frequencies) down", while pushing the artifacts (other arbitrary frequencies) of such processing outside the audible band.
Mental experiment: Suppose we are sampling ONE signal with two 24bit a/d's. One has a maximum input level of 4V p-p (in other words, it's referenced to 4V p-p) , and the other to 8V p-p (or 16/32/64/128...). When the input signal (at one sampling instant) exceeds 4V p-p, the second converter can still output a "correct" sample value for that sample. However, we are interested in outputting a digital stream that represents/corresponds to a reference voltage of 4V p-p(analog). So, we use the "meta data" afforded by the second converter to process the data from the first converter and make sure it fits into a 24bit/referenced-to-4Vp-p signal.
Oversampling limiting allows for a mechanism similar to this (in the frequency domain), because the signal is OVER sampled, we have the necessary "meta data" to work with.
This, I think, is best accomplished with very high sampling rates (128-256) of the original signal such as the output of an a/d converter, as opposed to upsampling an already decimated/filtered signal. It would require lots of processing power to do this kind of processing on a MHz range signal, which is why an FPGA or very fast DSP processor would be required. We are talking probably in the order of billions of computation per second!!
Maybe someone with a deeper understanding/knowledge of the problem can chime in, as I seem to be stuck thinking in terms of time-domain signals at this "instant". ;^) |